The use of scan-based techniques for testing integrated circuit (ICs) has become essential as IC component (e.g. transistor) density has increased. One reason for this is that due to size constraints, component density has far outstripped the number of electrical connectors, typically referred to as input/output pins, capable of being built into an IC. Thus, a circuit tester testing IC functionality via a limited number of pins encounters increasing difficulty in adequately reaching the voluminous number of state permutations and transitions provided by increased integration.
As a result, modern ICs are typically equipped with scannable logic elements to facilitate testing. A typical scannable IC includes one or more sets of state-holding elements (registers) interposed between circuit components and/or between circuit components and input/output pins. During normal operation, the state-holding elements are transparent to or incorporated as part of the functionality of the IC. In test mode, they are configurable as a serial shift register, or “scan-chain,” typically by linking the output of one state holding element to the input of another. The scan-chain permits scan test data to be serially shifted into and out of the state-holding elements via one or more input/output pins, thereby increasing the states reachable by a tester.
In a typical circuit test, a tester applies digital signal patterns to the pins of a device under test (“DUT”). The content, sequence and timing of test patterns are dependent on the architecture of the particular DUT, and are typically generated by the DUT manufacturer with the IC design software used for designing the DUT. There are two predominant types of test patterns used in the conventional art: scan test patterns and functional test patterns. Scan test patterns are bit patterns used to test selected subcircuits inside the device by establishing a particular one of many subcircuit states using a DUT's scan chain, followed by forcing a state transition from that state of the subcircuit to an expected second state, followed by verifying that the proper state transition occurred using the DUT's scan chain. Functional patterns are bit patterns typically applied in parallel to the input pins on the DUT to test functionality of the device as a whole. The bit patterns applied in parallel to the input pins of a device are called “functional test vectors” in the current art.
There are three predominant types of scan test patterns in the conventional art: a scan-in pattern, a scan-out pattern, and a scan-mask pattern. The scan-in pattern is the bit sequence serially shifted into a scan chain to configure the IC to a known starting state. The scan-out pattern is the bit sequence representing the expected state in a scan-chain resulting from the DUT's processing the scan-in patter. The scan-mask pattern is a bit pattern used for filtering out bits to be ignored in a particular scan test. The combination of the scan-in pattern, the scan-out pattern, and the scan-mask pattern is termed a “scan test vector” in the current art. An Automatic Test Pattern Generator (ATPG), of which many are well known in the art, is dominantly used to generate such scan-test vectors.
The steps in a typical scan test iteration are as follows: 1) the tester places the DUT in scan-test mode to configure the scannable logic into a scan-chain; 2) the tester serially shifts a scan-in pattern into the scan-chain with a scan clock via one or more DUT pins; 3) the tester switches the DUT to normal mode and applies one or more system clock signals to the DUT, possibly in combination with one or more functional patterns on the DUT input pins; 4) the DUT processes the test states in the scan-chain and the input pins; 5) the tester tests the states on the output pins, then switches the DUT back to scan-test mode; 6) the tester serially clocks out the states of the scan-chain with a scan clock for comparison with a scan-out pattern containing the expected results, ignoring states as indicated by the scan-mask pattern; and 7) the tester serially shifts in a new scan-in pattern with the scan clock, and repeats the above steps.
In the conventional art, a monolithic approach for storing and processing scan patterns predominates. In this approach, all of the scan patterns used in a test sequence are typically stored in sequential order in a contiguous block of tester memory, and the scan-out process that exhibits the results of one of the tests in the sequence overlaps the scan-in process of the next test in the sequence, thus reducing the overall test time. For each test scan-in pattern of the test sequence, the tester only reports whether the test passed or failed. Specifically, when a failure occurs in the test sequence, the captured test data does not coincide with predicted values. The failure is logged, and the next scan-in pattern is determined.
Known behaviors of small subcircuits inside IC's include photon emission and heating effects that behave slightly differently in the presence of defects than if the circuit is fabricated properly. Known detectors such as laser voltage probes or photon emission detectors can be used to sense such behaviors. In the current art, detailed diagnosis of failures makes use of the monolithic scan block by tediously extracting a failing scan vector from the monolithic block and repetitively executing that vector, perhaps in combination with a carefully and tediously constructed preconditioning set of functional vectors or scan vectors or both as may be required to repetitively force the same device or subcircuit state transition many hundreds or thousands of times in order to detect the slight differences that indicate the presence of a defect. The required repetition of a failing test to enable detection of these slight differences in behavior enables physical failure analysis (PFA), and is called a PFA loop.
However, the monolithic testing approach cannot easily vary the order of the scan-in test patterns in order to determine the proper voltage setting for each particular flash memory device during the test sequence. Also, the monolithic approach is unable to re-sequence scan patterns into new test sequences without reconstructing the entire monolithic combination of patterns. The monolithic approach lacks any level of indirection, or re-sequencing requiring new test scan-in patterns to be created and added to an overall test sequence.